In the field of integrated circuit there has for a long time been a need to ensure adequate protection of circuits against electrostatic discharges. In order to satisfy such a requirement for protection special protective structures have been developed, typically consisting of diodes or of MOS transistors. Generally, such structures are active during an electrostatic discharge limiting the consequent impulse of voltage and establishing a low resistance pathway towards the earth of the device.
Different strength tests against electrostatic discharges have also been defined, now considered standard, during which the devices with integrated circuit are subjected to stresses carried out according to certain methods to test their strength against various types of event that produce electrostatic discharges. A device with integrated circuit is considered strong if, subjecting such a device to a strength test, the structure for protecting from electrostatic discharges is not destroyed during the test and if the voltages inside the device thanks to the presence of such protective structures do not exceed values such as to damage the gate oxides of the devices of the integrated circuit.
In strength tests the events that are generally reproduced are those that simulate an unexpected contact of the device with integrated circuit, more specifically its external connection terminals (pins), with an element outside of the device that is at much different voltages to the voltages of the pins of the device.
The two most common strength test methods of a device with integrated circuit against electrostatic discharges are the so-called HBM (Human Body Model) test and the so-called CDM (Charged Device Model) test.
In a HBM test the contact between the device with integrated circuit and a human being is simulated. This is obtained by discharging a test capacity (for example having a value of 100 pF), charged in advance to a certain test voltage, between a pair of connection terminals (pins) of the device, one of which is connected to earth. In the HBM test in series with the capacity a resistance is foreseen that simulates the minimum resistance of the human body (about 1500 Ohm). The test is carried out for any pair of pins of the device.
In a CDM test a rubbing situation is simulated, connecting a capacity, previously charged to a certain test voltage and distinct from the voltage at which the device is charged, to a connection pin of the device without any of the remaining pins of the device being connected to earth. The test is carried out for all of the pins of the device. Unlike the HBM test, in the CDM test there is no resistance in series with the capacity.
In the HBM test, for a device to be considered strong it has to withstand test voltages of the order of 2000-4000 V, whereas in the CDM test resistance to a test voltage of about 500 V is an indication of a good level of strength.
In practice, in the HBM test the ESD protection structures are effective and also the time constants involved during the test are relatively large due to the resistance arranged in series with the condenser charged to the test voltage: this ensures that the different nodes of the integrated circuit have sufficient time available to reach the voltages set by the protection structures.
In CDM tests, on the other hand, there is a certain difficulty in sealing devices with integrated circuit, since the parts thereof in which circuit environments having separate power supply voltages interface are particularly lacking in strength.
The presence in an integrated circuit of two or more circuit environments fed by separate voltages is very frequent. Indeed, the power supplies are separated both when it is necessary to adapt a signal intended to operate with one power supply voltage to a different power supply voltage of a circuit, and to separate the two or more circuit blocks from one another in order to ensure a better distribution of the currents or in order to reduce a noise transfer between such blocks.
The causes of the particular lack of strength in CDM tests of integrated circuits having two or more circuit environments intended to operate with separate power supply voltages are briefly illustrated hereafter.
FIG. 1 schematically represents an example of an integrated circuit 1 including two circuit environments CE_1, CE_2 intended to operate with two separate power supply voltages.
In the example, the first circuit environment CE_1 is intended to be fed by a first power supply voltage applicable between two dedicated power supply terminals, for example corresponding to two connection pads VDD1, GND1.
The second circuit environment CE_2 is intended to be fed by a second power supply voltage, separate from the first power supply voltage, applicable between two dedicated power supply terminals, for example corresponding to two further connection pads VDD2, GND2.
The first circuit environment CE_1 comprises a logic circuit IV1_1, IV1_2 formed from two inverters connected in cascade and each made through a pair of MOS transistors. The logic circuit IV1_1, IV1_2 comprises an input terminal In1 suitable for receiving an input signal and an output terminal Ou1 to provide a corresponding output signal. Between the two power supply terminals VDD1, GND1 of the first circuit environment CE_1 there is a structure P1 for protecting against electrostatic discharges, of the conventional type. The capacity C1 between the two power supply terminals GND1, VDD1 represents an intrinsic capacity the presence of which is due to the process for making the integrated circuit. As is known, such a capacity can also assume high values (of the order of nF) particularly if the integrated circuit occupies a large area of substrate of semiconductive material.
Similarly, the second circuit environment CE_2 comprises a logic circuit IV2_1, IV2_2 formed from two inverters connected in cascade, each comprising a pair of MOS transistors. The logic circuit IV2_1, IV2_2 comprises an input terminal In2 connected to the output terminal Ou1 of the first circuit environment CE_1 and an output terminal Ou2 to provide an output signal. Between the two power supply terminals VDD2, GND2 of the second circuit environment CE_2 there is a structure P2 for protecting against electrostatic discharges, of the conventional type. The capacity C2 between the two power supply terminals VDD2, GND2 also represents an intrinsic capacity the presence of which is due to the process of making the integrated circuit.
Relative to the operation of the circuit 1 during a CDM strength test, presuming that the integrated circuit 1 is completely discharged and that a high voltage (for example 500 V) is applied to the power supply terminal GND1, the Applicant has observed the following.
Analysing the two circuit environments CE_1, CE_2 individually, each of them is substantially strong against electrostatic discharges. For example, in the first circuit environment CE_1 the capacity C1 is able to keep the voltage of the nodes corresponding to VDD1 and GND1 close together. If the voltage of the node GND1, as a result of the rapid application of the test voltage CDM of 500V, varies rapidly, in an ideal situation the capacity C1 tends to maintain its charge (in the example 0 V) taking the voltage of the node VDD1 to such a test voltage. In a real situation, the node VDD1 shall also encounter the parasite capacity of the other nodes (and of the substrate in particular) and for this reason the voltage of the node VDD1 will tend to differ from the voltage of the node GND1. However, if the difference in voltage becomes significant the protection structure P1 intervenes in order to contain such a difference. Should the intervention times of such a protection structure be long compared to the time constants of the variations as a consequence of the application of the test voltage in the CDM test, the protection may be not very effective. The same thing occurs due to the intrinsic transition for containing the variation in voltage due to the fact that the resistance of the protection structure P1 is not zero. In any case, should the efficiency of protection offered by the protection structure P1 be low, the protection can in any case be intrinsically ensured by the diodes of the drain and source diffusions of the components of the logic circuit. Moreover, overall these operate in parallel with the protection structure P1, improving its efficiency.
Relative to the second circuit environment CE_2, following the application of the test voltage to the first circuit environment CE_1, the Applicant has observed the following.
So that the second circuit environment CE_2 can feel the variation in voltage as a consequence of the application of the test voltage to the node GND1, such a variation must pass through connection pathways consisting of diodes between the first CE_1 and the second CE_2 circuit environment. Such diodes are, for example, back-to-back diodes between the earths, or else those towards the substrate typical of the production technology. The node GND2 has a high capacity towards the substrate, for example of the order of a few hundreds of picofarads, which must be charged through the pathways of back-to-back diodes. The connection pathways are fairly complex and difficult to evaluate, nevertheless since such diodes have finite resistance and the connection pathways are often made through long metallization runs, it has been observed that the connection pathways can reach typical overall resistances of tens of ohms. In this way a significantly different time constant is created compared to the time constant of the variation in voltage of the node GND1 as a consequence of the application of the test voltage. Consequently, the nodes GND2 and VDD2 tend to have a significantly different voltage to that of the node GND1. For this reason, the two MOS of the first inverter INV2_1 have a gate terminal at a voltage correlated to the voltage of the first circuit environment CE_1 and have drain and source terminals at voltages that move with the time constant associated with the node GND2. If a voltage difference is created such as to exceed the sealing characteristics of the gate oxides damage occurs. Clearly, in this case the circuit does not pass the CDM test.
This problem is made worse by the fact that in modern technological processes for producing integrated circuits there is a constant tendency to reduce the gate oxides, for which reason relatively low voltage differences are sufficient to cause the oxides to break.
If the evolution of ESD protection structures is such as to ensure a certain strength of integrated circuits in HBM tests, for the reasons described above this is just as much not the case for CDM tests, particularly when there are many circuit environments intended to operate with separate power supply voltages in the same integrated circuit.
Therefore, there is a need to make an integrated circuit [with high strength against] able to withstand electrostatic discharges and in particular discharges of the type simulated in CDM strength tests.